1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. In particular, the present invention relates to a method of manufacturing a semiconductor device by which characteristics of a semiconductor device can be evaluated in a wafer state.
2. Description of the Related Art
Compound semiconductors such as GaAs or the like have a higher electron mobility than that of Si, thereby having an excellent high frequency characteristic as compared with Si. Therefore, compound semiconductors are being applied to a field effect transistors (FET), which is a semiconductor element, such as a metal-semiconductor field effect transistor (hereinafter, referred to as MESFET) for high-speed operation utilizing a Schottky junction gate, and a semiconductor integrated circuit such as an integrated analog signal amplifier, digital signal amplifier or the like. Along with the recent increases in an operation speed of such a semiconductor element used as a semiconductor device or semiconductor integrated circuit. A semiconductor element having an operation frequency of 100 GHz is being put in practice today. As a result, the high frequency characteristic of a semiconductor element is becoming increasingly important.
Conventionally, various methods have been proposed as a method of manufacturing such a semiconductor element. These techniques widely used in manufacturing processes of mass production include, for example, a technique disclosed as prior art in Japanese Patent Laid-Open Publication No. Hei 2-022841. FIG. 1 is a cross sectional view showing a construction of a semiconductor pellet in this prior art. FIGS. 2A to 2D are perspective views showing a method of manufacturing this conventional semiconductor pellet in the order of process steps. The prior art will be described below with reference to FIG. 1 and FIGS. 2A to 2D.
First, an outline of the construction of this conventional semiconductor pellet will be explained with reference to FIG. 1. An MESFET is formed as a semiconductor element in this semiconductor pellet. In the semiconductor pellet 111 shown in FIG. 1, a source electrode 103 and drain electrode 104 are formed with a gate electrode 102 therebetween on a GaAs substrate 101. The gate electrode 102 and drain electrode 104 are connected to a gate lead electrode 106 and drain lead electrode 107 via apertures 105a, 105b, respectively, provided in an interlayer insulating film 105. On the other hand, the source electrode 103 is connected to a metal layer 109 for plating and gold plating layer 110 laminated on the rear surface of the GaAs substrate 101 via a through hole (via hole) 108 provided in the GaAs substrate 101. These laminated metal layer 109 for plating and gold plating layer 110 constitute a lead electrode of the source electrode 103. The gold plating layer 110 also functions as a plated heat sink (PHS). This semiconductor pellet 111 is thus constructed, having a length of about 0.5-2 mm.
A method of separating the semiconductor elements as chips will be explained below with reference to FIGS. 2A to 2D. The same component elements as those explained in FIG. 1 are designated by the same reference numerals through FIGS. 2A to 2D. As shown in FIG. 2A, a GaAs wafer 113 having semiconductor elements formed thereon is laminated onto a glass substrate 112 via a low melting point wax 114 with a surface of the GaAs wafer 113 on which the semiconductor elements are formed (hereinafter, referred to as front surface) facing the glass substrate 112 side. Then, a known method is employed to form the GaAs wafer 113 into a thin layer having a thickness of, for example, 40 xcexcm. Subsequently, through holes 108 (see FIG. 1) are formed in prescribed regions. Then, a metal film 109a for plating is formed on the whole surface of the GaAs wafer 113 on which the semiconductor elements are not formed (hereinafter, referred to as rear surface).
Subsequently, as shown in FIG. 2B, a gold plating layer 110 is selectively formed on the metal film 109a for plating by a known method using a photoresist pattern. Then, the metal film 109a for plating is patterned by using this gold plating layer 110 as a mask to form the aforementioned metal layer 109 for plating.
Subsequently, as shown in FIG. 2C, the GaAs wafer 113 is etched by using the gold plating layer 110 as a mask. Consequently, the GaAs wafer 113 is separated into chips to form semiconductor elements 115. Then, the low melting point wax 114 is melted by heating to a temperature equal to the melting point thereof or higher to peel off the glass substrate 112 from the semiconductor elements 115. Then, the semiconductor elements 115 are washed with an organic solvent.
Thus, a semiconductor pellet 111 composed of the semiconductor element 115, metal layer 109 for plating and gold plating layer 110 is formed as shown in FIG. 2D. The metal layer 109 for plating is formed on the rear surface of the semiconductor element 115 and the gold plating layer 110 is further formed on top thereof.
Subsequently, the high frequency (RF) characteristics of all the semiconductor pellets 111 separated into chips as described above are measured. According to the results of the measurement, the semiconductor pellets 111 are sorted into non-defectives and defectives (hereinafter, referred to as non-defectives/defectives screening).
In the prior art, as described above, the GaAs wafer 113 is separated into chips to form semiconductor pellets 111 and then electrical characteristics such as an RF characteristic and so forth of each semiconductor element 115 formed in the semiconductor pellet 111 are individually measured. In this method, however, a large number of processes are required for sorting the semiconductor pellets 111 into non-defectives and defectives, thereby increasing a manufacturing cost of the semiconductor pellets 111.
To solve this problem, not all the semiconductor pellets formed by separating one GaAs wafer into chips are subjected to measurement of electrical characteristics, but several of the semiconductor pellets formed from one GaAs wafer are selected to measure the electrical characteristics thereof and thus the quality of the whole GaAs wafer is judged. However, this method is not practical in mass production since defective semiconductor pellets are often mixed in the GaAs wafer determined as non-defective.
In addition, since electrical characteristics of an individual semiconductor element are measured in the prior art, inductance increases between electrodes of the semiconductor element and probes of a measuring apparatus during the measurement. The inductance of a ground electrode, in particular, increases and a problem arises that the electrical characteristics cannot be precisely measured.
An object of the present invention is to provide a method of manufacturing a semiconductor device by which non-defectives/defectives screening can be conveniently performed by measuring electrical characteristics of semiconductor elements and the semiconductor elements can be precisely screened by reducing inductance of a ground electrode.
A method of manufacturing a semiconductor device according to the present invention has the steps of: laminating a semiconductor wafer having a plurality of semiconductor elements on a first surface thereof onto a first wafer holding substrate by using a first adhesive so as to contact the first surface to the first wafer holding substrate; grinding a second surface of the semiconductor wafer on which the semiconductor elements are not formed to form a semiconductor wafer of a prescribed thickness; coating a first conductive layer on the whole second surface of the semiconductor wafer; selectively forming a second conductive layer on the first conductive layer in regions aligning to the semiconductor elements formed on the first surface of the semiconductor wafer; laminating a second wafer holding substrate on the first conductive layer and second conductive layer by using a second adhesive; melting the first adhesive to peel off the first wafer holding substrate from the semiconductor wafer and expose the first surface of the semiconductor wafer; selectively etching the semiconductor wafer from the exposed surface so as to be separated into semiconductor elements and partially expose the first conductive layer; evaluating the semiconductor elements so as to be sorted into non-defectives and defectives; selectively etching the exposed portion of the first conductive layer; and removing the second adhesive to peel off the second wafer holding substrate from the first and the second conductive layers.
Another method of manufacturing a semiconductor device according to the present invention has the steps of: laminating a semiconductor wafer having a plurality of semiconductor elements on a first surface thereof onto a first wafer holding substrate by using a first adhesive so as to contact the first surface to the first wafer holding substrate; grinding a second surface of the semiconductor wafer on which the semiconductor elements are not formed to form a semiconductor wafer of a prescribed thickness; coating a first conductive layer on the whole second surface of the semiconductor wafer; selectively forming a second conductive layer on the first conductive layer in regions aligning to the semiconductor elements formed an the first surface of the semiconductor wafer; selectively etching the first conductive layer by using the selectively formed second conductive layer as a mask; laminating a second wafer holding substrate on the second conductive layer by using a second adhesive, which is a conductor; melting the first adhesive to peel off the first wafer holding substrate from the semiconductor wafer and expose the surface of the semiconductor wafer; selectively etching the semiconductor wafer from the exposed surface so as to be separated into semiconductor elements and partially expose the second adhesive surface; evaluating the semiconductor elements so as to be sorted into non-defectives and defectives; and removing the second adhesive to peel off the second wafer holding substrate from the second conductive layer.
The first conductive layer may be electrically connected to a ground electrode of the semiconductor element formed on the semiconductor wafer surface, for example, a source electrode of an MESFET. Then, in screening of the semiconductor elements, the first conductive layer before selectively etched may be connected to a ground potential to measure electrical characteristics of the semiconductor element. Or, the first conductive layer may be electrically connected to a ground electrode of the semiconductor element formed on the semiconductor wafer surface, for example, a source electrode of an MESFET. Then, in screening of the semiconductor elements, the second conductive layer, which is a conductor, may be connected to a ground potential to measure electrical characteristics of the semiconductor element.
Furthermore, the semiconductor element may be a field effect transistor. Electrical characteristics measured in the non-defectives/defectives screening of a field effect transistor preferably include a high frequency characteristic. The reason for this is that the high frequency characteristic becomes important as an operation speed of the semiconductor element is increased.
The second adhesive, which is a conductor, may be a conductive paste such as a silver paste. The first adhesive can be a low melting point wax. Furthermore, at least one of the first wafer holding substrate and second wafer holding substrate may be a transparent substrate. This transparent substrate may be constituted by a glass plate, quartz plate or sapphire plate.
In the present invention, since the first conductive layer is connected to the ground electrode of the semiconductor element formed on the semiconductor wafer, for example, the source electrode of the field effect transistor, inductance of the ground electrode of this semiconductor element can be reduced to about the same level as that of a semiconductor element mounted in a package as a product. As a result, inductance on the source side of the semiconductor element is greatly reduced and thus a high frequency characteristic can be precisely measured.
In addition, since the first conductive layer is connected to the ground electrode of each semiconductor element, only one ground electrode can be used in screening of the semiconductor elements. Since a plurality of semiconductor elements formed on the semiconductor wafer before separated into chips are sorted into non-defectives and defectives and then the chips are separated, the semiconductor elements can be easily handled in screening of the semiconductor elements. As a result, the non-defectives/defectives screening can be precisely and conveniently performed for all the semiconductor elements formed on the semiconductor wafer. Therefore, the method of manufacturing a semiconductor device according to the present invention can be applied to mass production of semiconductor devices.